Sense. Reason. Act. Scale.
The Physical AI compute platform that adapts as models change and scales as systems grow.
Physical AI is a System Workload, Not an Isolated Model.
Physical AI is not one model running fast. It is a continuous loop—sense, understand, retrieve, reason, plan, act, and verify—combining neural inference with sensor processing, control flow, application logic, and safety supervision. These workloads are concurrent, irregular, and latency-sensitive. A platform optimized only for peak model throughput leaves the rest of the system waiting.
RAIDEN™ is a scalable, energy-efficient chiplet platform designed to run the complete workload and scale the entire system. At its core, our new DNA-X® architecture preserves the runtime-reconfigurable benefits from the previous generation, while adding entirely new microcode-programmable matrix and vector processing engines. This extends adaptability beyond neural inference to evolving tensor mathematics, signal processing, and irregular computations. On-package 64-bit RISC-V cores run application logic, retrieval, orchestration, control, and safety functions through a shared memory architecture synchronized with DNA-X.
RAIDEN scales the entire execution environment for Physical AI, not just TOPS. Heterogeneous compute, memory, and connectivity scale together—from one to four compute dies, up to 256 GB of LPDDR5X memory, 548 GB/s of memory bandwidth, 1.54 TB/s of package-local die-to-die bandwidth, and up to 800 GB/s of bidirectional chip-to-chip connectivity.
Run the whole workload. Adapt as it changes. Scale beyond one chip.
Why RAIDEN Platform
1Runs the whole agentic loop, not just the model
Physical AI is a loop of multiple, irregular, latency-sensitive operations around one or more AI models - control flow, retrieval, sensor processing. RISC-V application cores and DNA-X’s programmable matrix and vector engines, together deliver deterministic performance across workloads.
2AI evolves. RAIDEN evolves with it
Microcode-programmable DNA-X engines, RISC-V cores, and dedicated LDPC accelerators combine AI and non-AI compute on one heterogeneous platform. DNA-X adapts to new operators and model architectures through microcode, keeping RAIDEN optimized as the AI landscape evolves.
3One chip has a limit. RAIDEN scales
One to four compute dies on a UCIe fabric unified at 1.5 TB/s and up to 800 GB/s of chip-to-chip connectivity, scales beyond the limits of reticle constrained monolithic designs. One integration effort from onboard autonomy to the edge data centers.
4Your models come with you
MERA™ software is in production on SAKURA-II today, with native compatibility with Hugging Face, ONNX, ExecuTorch and TensorFlow Lite, and support for x86, Arm and RISC-V hosts. MERA 3.0 expands its software features for RAIDEN; New silicon, not a new toolchain.
Physical AI compute platforms can stall when workloads exceed available memory, memory bandwidth cannot feed the compute, or multiple dies cannot exchange data fast enough to operate as a unified system. RAIDEN is designed to address all three.
Up to 256 GB of LPDDR5X keeps large multimodal models and their supporting pipelines resident, and 548 GB/s of memory bandwidth keeps them moving. Up to 1.54 TB/s of die-to-die bandwidth keeps all four compute dies operating as one unified system, sharing on-chip SRAM across a single compute and memory fabric. The result is less swapping, partitioning, and aggressive quantization, enabling complete Physical AI workloads to run on one tightly integrated heterogeneous compute platform rather than a collection of isolated accelerators, scaling from intelligent machines to edge data centers. Configurable power settings let the platform address different performance and deployment requirements.
Scale Agentic AI at the Edge.
Get the all the details in the RAIDEN-X4 product brief.
| Specification | RAIDEN-X4 |
|---|---|
| Dies | 4 |
| Programmable Matrix Processing* | 3,360 TFLOPS* |
| Programmable Vector Processing** | 64 vector cores |
| 64-bit RISC-V Cores on-package*** | 32-cores |
| High Bandwidth Shared Memory Hub | 15.6 TB/s |
| LPDDR5X Memory Capacity / Bandwidth | 256 GB / 548 GB/s |
| Die-to-Die Bandwidth | 1.54 TB/s |
| PCIe Connectivity | up to 4 x Gen 6.0 x8 |
| External Chip to Chip Connectivity | up to 800 GB/s bidirectional |
| Integrated LDPC Encode / Decode Cores | 4 encode cores, 40 decode cores |
DNA-X Architecture (per RAIDEN die)
* Supports FP4 sparse compute with 2:4 sparsity. Natively supported precisions include INT4, FP4, INT8, FP8, FP16, BF16, and FP32, with mixed-precision operation also supported. Compatible with MXFP8, MXFP4, and NVFP4. Microcode-programmable to support new AI operators. ** Provides DSP-like functionality through programmable microcode, enabling non-AI workloads and computationally intensive mathematical operations. *** RISC-V application cores are Linux-capable and can run a full operating system, either independently or in combination with the other heterogeneous compute cores.
Target Deployments: RAIDEN in Action
Physical AI shows up in different places, a robot's onboard compute, a factory inspection line, an on-premise inference node(s). What they share is a workload that outgrows peak TOPS: large multimodal models, live sensor streams, and concurrent pipelines where data movement becomes the limit. With RAIDEN, one architecture covers the range, from intelligent machines to edge data centers.
Sense. Reason. Act. Scale.
Explore our Exclusive Early Access Program
Bring your workload. We’ll run it on RAIDEN.
Early Access partners receive priority consideration for customer samples when sampling opens in Q1 2027, ahead of production in H2 2027. Participation is limited and selected by application fit.