Latest Research

Discovering a new pareto frontier of performance vs accuracy, design implemented on Xilinx ZCU102 FPGA

Meeting the strict latency and energy constraints of Edge AI with fully automated search across deep neural network models and hardware accelerator designs.

W. Jiang et al. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, April 2020 (arXiv 2019)

Title: Hardware/Software Co-exploration of Neural Architectures

Abstract: We propose a novel hardware and software co-exploration framework for efficient neural architecture search (NAS). Different from existing hardware-aware NAS which assumes a fixed hardware design and explores the neural architecture search space only, our framework simultaneously explores both the architecture search space and the hardware design space to identify the best neural architecture and hardware pairs that maximize both test accuracy and hardware efficiency. Such a .......

H. R. Zohouri and S. Matsuoka, 2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), SC19

Title: The Memory Controller Wall: Benchmarking the Intel FPGA SDK for OpenCL Memory Interface

Abstract: Supported by their high power efficiency and recent advancements in High Level Synthesis (HLS), FPGAs are quickly finding their way into HPC and cloud systems. Large amounts of work have been done so far on loop and area optimizations for different applications on FPGAs using HLS. However, a comprehensive analysis of the behavior and efficiency of the memory controller of FPGAs is missing in literature, which ......

Talks & Resources

Dr. Sakya Dasgupta's (CEO) talk at SGInnovate
event on "Breaking Down AI at the Edge", April 2020