Latest Research

Discovering a new Pareto frontier of deep neural network performance vs accuracy, co-designed on real hardware.

W. Jiang et al., "Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search With Hot Start", IEEE Tans. Computer-Aided Design of Integrated Circuits and Systems, Oct 2020.
(paper link)

EdgeCortix Dynamic Neural Accelerator (DNA) AI Processor architecture -
"Energy-Efficient, Reconfigurable and Scalable AI Inference Accelerator for Edge Devices"

The Linley Group- Microprocessor April 2021
W. Jiang et al. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, April 2020 (arXiv 2019)

Title: Hardware/Software Co-exploration of Neural Architectures

Abstract: We propose a novel hardware and software co-exploration framework for efficient neural architecture search (NAS). Different from existing hardware-aware NAS which assumes a fixed hardware design and explores the neural architecture search space only, our framework simultaneously explores both the architecture search space and the hardware design space to identify the best neural architecture and hardware pairs that maximize both test accuracy and hardware efficiency. Such a .......

H. R. Zohouri and S. Matsuoka, 2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), SC19

Title: The Memory Controller Wall: Benchmarking the Intel FPGA SDK for OpenCL Memory Interface

Abstract: Supported by their high power efficiency and recent advancements in High Level Synthesis (HLS), FPGAs are quickly finding their way into HPC and cloud systems. Large amounts of work have been done so far on loop and area optimizations for different applications on FPGAs using HLS. However, a comprehensive analysis of the behavior and efficiency of the memory controller of FPGAs is missing in literature, which ......

Talks & Resources

"Edgecortix Dynamic Neural Accelerator-F-Series and MERA compiler Product Demo"

Presenter: Hamid R. Zohouri
Director of Product, EdgeCortix
Presented at the Edge AI and Vision Alliance organized Innovation Forum Q1 2021
"Dynamic Neural Accelerator® Bitstream & MERA™ Compiler for Low Latency Deep Neural Network Inference"
Presenters: Naoki Shibuya & Nikolay Nez
Presented at PALTEK Corporation organized AI Webinar, February 2021
Dr. Sakya Dasgupta's (CEO) talk at SGInnovate
event on "Breaking Down AI at the Edge", April 2020